HCX C1
Composable chiplet computeModular dies, advanced packaging and unified fabric for configurable compute.
- Decoupled compute and I/O dies
- High-bandwidth in-package fabric
- Composable designs across system scales
HOLYCORESFROM MATERIAL TO COMPUTE
AI-generated process illustrations
HELIOS / HOLYCORES AI SILICON
Designed in-house,
from silicon up.
An in-house foundation spanning compute cores, on-chip memory, dataflow, fabric and software interfaces for datacenter and edge AI.
WHY OWN SILICON
A chip is not isolated. It is where the platform begins.
HOLYCORES starts with real models and deployment constraints, co-designing compute cores, memory hierarchy, data movement, package fabric, compiler and runtime into one evolvable foundation. The objective is useful compute, programmability, efficiency and system scale—not unverified peak numbers.
PLANNED SILICON PORTFOLIO
One architecture, three silicon boundaries.
HCX E1
Edge AI SoCInference, control and high-speed I/O for robotics, vision and field intelligence.
- Efficient local inference
- Sensor and media data paths
- Secure boot, isolation and device management
HCX D1
Datacenter AI compute siliconScalable compute for model inference, fine-tuning and dense server platforms.
- Cooperative tensor, vector and scalar execution
- Hierarchical on-chip storage and memory interfaces
- High-speed die-to-die and scale-out fabric
COMPUTE ARCHITECTURE
Organize every operation around dataflow.
Programmable compute array
Tensor, vector and scalar resources support mainstream operators and custom kernels.
Layered on-chip memory
Local stores, shared cache and external memory paths reduce unnecessary movement.
Dataflow fabric
Low-latency movement reflects operator dependencies, parallelism and scale-out patterns.
Hardware virtualization
Isolation, scheduling and telemetry support multi-model and multi-tenant operation.
MEMORY / FABRIC / PACKAGE
Performance comes from the full data path.
Silicon definition considers on-chip SRAM, external memory, host interfaces, die-to-die links and advanced packaging together. Bandwidth, capacity, latency, power and manufacturability must be validated within one system boundary.
Keep highly reused data close to execution.
Plan for weights, KV cache and intermediate activations.
Connect in-package, board-level and system-level movement.
HARDWARE / SOFTWARE CO-DESIGN
Software enters at the start of silicon definition.
- Workload characterizationAnalyze operators, shapes, precision, bandwidth and communication.
- Architecture modelingEvaluate compute, memory and fabric choices with performance models.
- Compiler mappingMap graphs into executable dataflow and kernels.
- System feedbackUse real workloads to refine hardware and software.
ENGINEERING EVIDENCE
Build evidence from models through post-silicon.
Workload characterization, performance modeling and power estimation.
Functional and formal verification, timing, power and testability.
Characterization, packaging, board, stability and reliability validation.
Accuracy, performance, scaling, compatibility and endurance testing.
FAQ
About HOLYCORES AI silicon
Are these chips in production?+
This page describes in-house R&D directions and planning boundaries. Tape-out, production, availability and final specifications will be announced as engineering matures.
How do the chips relate to NOVA and SPARK?+
Silicon is the compute foundation. NOVA and SPARK package that capability into datacenter accelerators and edge products.
How can a team join validation?+
Bring target models, baselines, deployment conditions and success criteria to define an evaluation path together.
START WITH A REAL WORKLOAD