Unified compute model
Reuse model and operator work across deployment targets.

AI ACCELERATOR
An open acceleration platform for datacenter training and inference.
NOVA ACCELERATOR CARDS



COMPARE NOVA MODELS
| Planning dimension | NOVA N100A | NOVA N200A | NOVA N200P |
|---|---|---|---|
| Form factor | Single-chip active card | Dual-chip active card | Dual-chip passive card |
| Relative compute scale | 1× baseline | Approx. 2× N100A | Approx. 2× N100A |
| Target memory | 24 GB | 48 GB | 48 GB |
| Host interface | PCIe 5.0 ×16 | PCIe 5.0 ×16 | PCIe 5.0 ×16 |
| Card fabric | Host PCIe | 2× HC-Fabric | 2× HC-Fabric |
| Target board power | Up to 225 W | Up to 350 W | Up to 300 W |
| Cooling | Dual-slot active | 2.5-slot active | Dual-slot passive |
| Target deployment | Developer workstations, inference servers | High-throughput inference, multi-card nodes | High-density rack servers |
Planning targets may change following silicon, board, thermal, and system validation. Final availability, compatibility, and specifications will be defined in future product materials.
DESIGN PERSPECTIVE
Reuse model and operator work across deployment targets.
Co-design compute, fabric, cooling, and operations around real workloads.
Start with validation, then expand to clusters and edge fleets.
Every engagement connects architecture, software, validation, and production operations.
ENGAGEMENT MODEL
FAQ
These pages describe product direction. Availability, specifications, and schedules will be confirmed in formal product materials.
It reduces repeated engineering when models move between deployment environments.
The planned path starts with development and validation before scaling to production.
CHOOSE YOUR PERSPECTIVE
Understand platform scope, deployment choices, and the long-term path.
Follow this path →Evaluate compute, fabric, software, operations, and facility constraints.
Follow this path →Focus on model entry points, operators, tooling, and portability.
Follow this path →TECHNICAL EVALUATION
| Dimension | Question | Validation |
|---|---|---|
| Compute architecture | Adapt to different models and precision strategies | Build utilization and accuracy baselines with representative workloads |
| Memory hierarchy | Reduce avoidable movement and bandwidth stalls | Profile working sets and end-to-end bottlenecks |
| Scale-out fabric | Grow from device to node and cluster | Validate topology, communication, and scaling efficiency |
| Software stack | Map framework models reliably to hardware | Check coverage, correctness, and tunability |
| System engineering | Balance power, cooling, density, and serviceability | Validate against the target facility and workload |
| Operations | Deploy, observe, upgrade, and diagnose | Establish telemetry, health, version, and rollback workflows |
WORKLOAD MAP
Throughput, communication, precision, and long-run stability.
Response time, generation rate, concurrency, and utilization.
Data boundaries, operational control, auditability, and lifecycle.
Local latency, power, interfaces, and environment.
ADOPTION PATH
Create a baseline with representative models and evaluation systems.
Integrate with customer security, datacenter, and operational practices.
Expand clusters or edge fleets against capacity and service goals.
PRODUCTION READINESS
Health, fault isolation, recovery, and long-run validation.
Boot, identity, access, update, and data-boundary planning.
Telemetry that connects model behavior to system state.
Versioning, compatibility, rollback, maintenance, and support.
RESOURCES & STATUS
Product direction, architecture principles, workloads, and evaluation framework on this site.
Workload definition, environment requirements, success metrics, and test planning.
Specifications, compatibility, SDKs, docs, release notes, and validated model status will follow maturity.
Scalable compute cores and on-chip fabric map flexibly to different models.
A standard accelerator form factor supported by HOLYFLOW.
READY TO BUILD?